Deep-submicron IC Physical Design Floorplanning, Place and Route engineering consultant, with extensive VLSI design experience, from computer architecture to fabrication. As a consultant, I helped several new IC startups (Jaldi Semiconductor, Globespan) successfully launch their first ICs, with physical design of their own multi-million-gate ASICs using customer-owned-tooling flows, while training brand new design teams on physical design flows and methodologies. Also helped established IC design vendors develop their next-generation chips, such as the Xenos graphics chip for the X-Box 360 (ATI, now AMD). Developed hierarchical reuse methodologies to systematically break down large multi-million gate projects into manageable tasks.
Expert applications engineer for Cadence Encounter and NanoRoute, with skills in Synthesis, Timing Analysis, Floorplanning, Place, Route, Power-Grid, Sign-off, Hierarchical Design, Signal Integrity analysis and repair, Timing optimization.
Designed physical layout of XBox 360 graphics processor. Performed Floorplanning/Place/Route for 90nm Xenos GPU. Conducted physical design of the core pixel-processor (about 80% of the chip) using Cadence Encounter, NanoRoute, and Silicon Ensemble, and Synopsys Physical Compiler. Performed timing and signal integrity analysis with Cadence CeltIC and Synopsys PrimeTime-SI. Optimized LEF library files for routing density and signal integrity. Performed DRC checks with Mentor Calibre.
Designed physical layout of digital television video processor chip. Floorplanning/Place/Route for a 130nm video processor ASIC for a new startup's first chip. Developed a novel power-grid design algorithm based on emulated sheet resistance of the power grid over the full chip. Trained a team of new-grads and co-ops in the design of an ASIC, while assisting experienced architects in optimizing the flow for reuse methodologies. Synthesized design with Ambit BuildGates/PKS. Floorplanned chip with Design Planner. Placed and Routed with Silicon Ensemble.
Developed a LEF/DEF and GDS viewing tool using OpenGL and TrollTech QT libraries on Linux, Solaris, and Mac OS. Incorporated OpenAccess database usage as well.
Primarily functioned as an on-site applications and methodology engineer for place and route tools, such as Encounter and Silicon Ensemble.
Performed lead physical design tapeout roles in various multi-million gate client projects such as ATI Rage 6 & Globespan, and as an on-site expert Cadence applications engineer for support of tools sales and flow development and optimization at many client sites, such as IBM/Lucent/Jaldi/ATI.
Primary tools I've worked with include: floorplanning and implementation with Cadence's SoC Encounter/First Encounter platform, routing with NanoRoute and Cadence Chip Optimizer & Space Based Router, power-grid design with VoltageStorm, synthesis with Cadence RTL Compiler and Synopsys Design Compiler, timing analysis with Cadence Encounter Timing System and Synopsys PrimeTime-SI, functional verification with Encounter Conformal Equivalence Checker, extraction with Cadence QRC, library cell layout with Virtuoso, sign-off with Mentor Calibre.
Performed synthesis, timing analysis, floorplanning, place, route, power-grid design, DRC sign-off, flat and hierarchical design, signal integrity analysis and repair, timing optimization, LEF tech file optimization.
Spent several years as IBM-Cadence on-site AE to bridge the interface between the IBM EDA design tools, such as Einstimer and ChipBench, and Cadence tools. Developed EDA C++ tools with OpenAccess database. Developed optimized technology and LEF files for IBM Foundry to improve the QoR of results (timing, area, signal integrity, power, yield) using Cadence tools.
Developed and architected a hardware emulator for Motorola's Iridium satellite phone network system. Wrote and synthesized VHDL for Altera FPGAs to emulate the ATM communications network used by the Iridium satellites, including protocol debugging and fault tolerance. Incorporated Hamming code in the network. Fabricated and debugged the emulator hardware in the test labs for delivery to Motorola.
Designed and architected a military satellite-based hyper-spectral image processor. Project included designing an array of 32 Analog Devices SHARC DSPs to create a multi-GFLOP processor core to perform the core dot-product matrix multiplication algorithm.
Designed .75 megapixel CMOS image sensor chip for consumer digital cameras. Helped design and lay out the pixel cell in Cadence Virtuoso. Placed and routed the on-chip controller in Cadence Cell3. Performed analog circuit design and simulation of the correlated double-sampling column 10-bit A/D converter using Cadence Virtuoso.
Designed central processor unit of a massively parallel-processing-system half-megawatt supercomputer. Performed both circuit and physical design design of the core data path in LSI Logic EDA tools using .5 micron and wafer-scale-integration technologies. Hand placed over 16000 standard cells to match the datapath of the cryptography processing algorithm, with optimizations for area and speed. Subdivided the design hierarchically to reduce development time. Achieved the smallest possible area for the datapath at the faster-than-expected speeds.
Performed physical design of standard cells in Cadence Virtuoso. Developed LEF libraries with Abstract generators for standard cells.
Assisted researchers in new development of SOI wafers using bonding-and-etchback technique.
Worked on internal projects using the nascent"World Wide Web" protocol from CERN/W3C, incorporating hypertext and graphics, for display on the Mosaic browser on Solaris operating systems.